1. Field of the Invention
The present invention relates generally to programmable logic devices, and more particularly, to zero-power logic cells implemented with field effect transistors for use in programmable logic devices having minimized static power dissipation.
2. Discussion of the Related Art
Referring to FIG. 1, an example programmable logic device is a programmable AND gate 100 of the prior art. The programmable AND gate 100 includes a first input node 102 for inputting a first input signal, A, and a second input node 104 for inputting a second input signal, B. The first input signal, A, is coupled through a first inverter 106 and a second inverter 108 to the gate of a first NMOSFET (N-channel metal oxide semiconductor field effect transistor) 110. The complement of the first input signal, designated as A*, (i.e., the output of the first inverter 106) is coupled to the gate of a second NMOSFET (N-channel metal oxide semiconductor field effect transistor) 112.
Similarly, the second input signal, B, is coupled through a third inverter 114 and a fourth inverter 116 to the gate of a third NMOSFET (N-channel metal oxide semiconductor field effect transistor) 118. The complement of the second input signal, designated as B*, (i.e., the output of the third inverter 114) is coupled to the gate of a fourth NMOSFET (N-channel metal oxide semiconductor field effect transistor) 120.
A first programmable switch 122 is coupled between the drain of the first NMOSFET 110 and an output node 130, and a second programmable switch 124 is coupled between the drain of the second NMOSFET 112 and the output node 130. Similarly, a third programmable switch 126 is coupled between the drain of the third NMOSFET 118 and the output node 130, and a fourth programmable switch 128 is coupled between the drain of the fourth NMOSFET 120 and the output node 130. In addition, a current source 132 is coupled to the output node 130 for charging the output node 130 when the output signal at the output node 130 turns to a logical high state.
For operation of the programmable AND gate 100 of FIG. 1, the first, second, third, and fourth switches 122, 124, 126, and 128 are programmable to be switched open or closed. One of the first and second programmable switches 122 and 124 is programmed to be open, and the other is programmed to be closed. Similarly, one of the third and fourth programmable switches 126 and 128 is programmed to be open, and the other is programmed to be closed.
The output node 130 of the programmable AND gate 100 provides an AND operation of one of the first input signal, A, or the complement of the first input signal, A*, and one of the second input signal, B, or the complement of the second input signal, B*. If the first switch 122 is programmed to be closed with the second switch 124 being programmed to be open, then the programmable AND gate 100 provides an AND operation with the complement of the first input signal, A*, instead of the first input signal, A. On the other hand, if the first switch 122 is programmed to be open with the second switch 124 being programmed to be closed, then the programmable AND gate 100 provides an AND operation with the first input signal, A, instead of the complement of the first input signal, A*.
Similarly, if the third switch 126 is programmed to be closed with the fourth switch 128 being programmed to be open, then the programmable AND gate 100 provides an AND operation with the complement of the second input signal, B*, instead of the second input signal, B. On the other hand, if the third switch 126 is programmed to be open with the fourth switch 128 being programmed to be closed, then the programmable AND gate 100 provides an AND operation with the second input signal, B, instead of the complement of the second input signal, B*.
Thus, in the example illustration of FIG. 1, since the first switch 122 is programmed to be closed while the second switch 124 is programmed to be open, the programmable AND gate 100 provides an AND operation with the complement of the first input signal, A*, instead of the first input signal, A. Also, since the third switch 126 is programmed to be open while the fourth switch 128 is programmed to be closed, the programmable AND gate 100 provides an AND operation with the second input signal, B, instead of the complement of the second input signal, B*.
Thus, the output node 130 provides an output signal=A*xc2x7B. Referring to FIG. 1, only in the case when the first input signal, A, is a logical low state and the second input signal, B, is a logical high state, all of the first, second, third, and fourth NMOSFETs 110, 112, 118, and 120 do not conduct current away from the output node 130. Thus, the current from the current source 132 charges up the output node 130 to a logical high state in that case. For any other logical states of the first and second input signals, A and B, at least one of the first NMOSFET 110 and the fourth NMOSFET 120 conducts current out of the output node 130 to couple the output node 130 to ground such that a logical low state is formed at the output node 130.
In the prior art programmable AND gate 100 of FIG. 1, a constant amount of current from the current source 132 is dissipated when at least one of the first NMOSFET 110 and the fourth NMOSFET 120 conducts current out of the output node 130 to couple the output node 130 to ground. Such constant current flow results in disadvantageous power dissipation. In addition, device dimensions are constantly scaled down with advancement of IC (integrated circuit) technology. However, as supply voltages are further scaled down along with device dimensions, the noise margin of the prior art programmable AND gate 100 of FIG. 1 disadvantageously decreases to deteriorate the performance of the AND gate 100. In addition, the steady state current of the current source 132 does not necessarily scale down with device dimensions such that the prior art programmable AND gate 100 of FIG. 1 still has disadvantageous steady state power dissipation even with scaling down of device dimensions.
Thus, a mechanism is desired for implementing programmable logic devices such as programmable AND gates and programmable OR gates with minimized static power dissipation and with further scalability of device dimensions and supply voltages.
Accordingly, in a general aspect of the present invention, zero-power logic cells are implemented in CMOS (complementary metal oxide semiconductor) technology. Such zero-power logic cells advantageously form part of programmable logic devices such as programmable AND, OR, NAND, or NOR gates with minimized power dissipation.
In a first embodiment of a zero-power logic cell of the present invention, a first pair of stacked P-channel field effect transistors are coupled between VCC1 and an output node, and a second pair of stacked P-channel field effect transistors are coupled between VCC2 and the output node. A first pair of stacked N-channel field effect transistors are coupled between VSS1 and the output node, and a second pair of stacked N-channel field effect transistors are coupled between VSS2 and the output node.
A gate of a first P-channel transistor of the first pair of P-channel transistors is coupled to an output of a first memory cell, and a second P-channel transistor of the first pair of P-channel transistors has a gate coupled to a first input signal and has a drain coupled to the output node. A first N-channel transistor of the first pair of N-channel transistors has a gate coupled to the first input signal and has a drain coupled to the output node, and a gate of a second N-channel transistor of the first pair of N-channel transistors is coupled to a second input signal.
In addition, a gate of a third P-channel transistor of the second pair of P-channel transistors is coupled to an output of a second memory cell, and a fourth P-channel transistor of the second pair of P-channel transistors has a gate coupled to the second input signal and has a drain coupled to the output node. A third N-channel transistor of the second pair of N-channel transistors has a gate coupled to the output of the first memory cell and has a drain coupled to the output node, and a gate of a fourth transistor of the second pair of N-channel transistors is coupled to the output of the second memory cell. The drains of the second and fourth N-channel transistors are coupled together.
The logic cell is programmable when the first and second memory cells are electrically erasable and programmable. In a functional mode, an input selection circuit couples a logic cell input signal as the first input signal and the complement of the logic cell input signal as the second input signal. In that case, the output signal at the output node is one of a logical low state, a logical high state, the logic cell input signal, or the complement of the logic cell input signal, depending on the outputs of the memory cells.
Such a logic cell is used to particular advantage as part of a programmable logic device, and such a first embodiment of the zero-power logic cell is especially advantageous for forming part of a programmable OR gate or a programmable NOR gate during a verify mode. During the verify mode, the input selection circuit couples a first logic state as the first input signal and a second logic state as the second input signal with the first logic state being independent of the second logic state for verifying the outputs of the memory cells within the logic cell.
In a second embodiment of the zero-power logic cell of the present invention, the gate of the first P-channel transistor of the first pair of P-channel transistors and the gate of the third N-channel transistor of the second pair of N-channel transistors are coupled to the second input signal (instead of to the output of the first memory cell). In addition, the gate of the second N-channel transistor of the first pair of N-channel transistors and the gate of the fourth P-channel transistor of the second pair of P-channel transistors are coupled to the output of the first memory cell (instead of to the second input signal). Furthermore, the drains of the first and third P-channel transistors are coupled together.
With such a second embodiment of the logic cell, in the functional mode, when the input selection circuit couples the logic cell input signal as the first input signal and the complement of the logic cell input signal as the second input signal, the output signal at the output node is one of a logical low state, a logical high state, the logic cell input signal, or the complement of the logic cell input signal, depending on the outputs of the memory cells.
Such a logic cell is used to particular advantage as part of a programmable logic device, and such a second embodiment of the zero-power logic cell is especially advantageous for forming part of a programmable AND gate or a programmable NAND gate during a verify mode. During the verify mode, the input selection circuit couples a first logic state as the first input signal and a second logic state as the second input signal with the first logic state being independent of the second logic state for verification of the outputs of the memory cells within the logic cell.
Such first and second embodiments of the logic cells are implemented in CMOS (complementary metal oxide semiconductor) technology when the first and second pairs of P-channel transistors are comprised of PMOSFETs (P-channel Metal Oxide Semiconductor Field Effect Transistors), and when the first and second pairs of N-channel transistors are comprised of NMOSFETs (N-channel Metal Oxide Semiconductor Field Effect Transistors).
In this manner, the logic cells of the present invention are implemented in CMOS technology without use of any current source. Rather, the logic cells of the present invention operate to provide logic levels with zero power dissipation. In addition, the logic cells in the present invention are further scalable.
Furthermore, with such first and second embodiments of the zero-power logic cells of the present invention, the verification of the outputs of the memory cells is advantageously performed directly through such logic cells such that a separate verification unit is not needed. A separate verification unit may disadvantageously require additional chip space. Rather, with use of the first and second embodiments of the logic cells of the present invention for implementing programmable AND, NAND, OR, or NOR gates, verification of the outputs of the memory cells for each of the logic cells may be performed with just the programmable gates without any separate additional verification unit, to save chip space.
These and other features and advantages of the present invention will be better understood by considering the following detailed description of the invention which is presented with the attached drawings.